Write a One-Hot SystemVerilog Constraint Without $onehot

Write a SystemVerilog constraint for an N-bit randomized variable a such that a is one-hot: exactly one bit is 1 and all other bits are 0. Requirements: Do not use the SystemVerilog built-in function $onehot. N >= 1. The all-zero value must be excluded. For example, when N = 4, valid values are 4'b0001, 4'b0010, 4'b0100, and 4'b1000. Example Input N=1 Output 合法随机结果：1'b1